This invention relates to the field of digital signal processing, and in a particular to a method and apparatus for implementing a high-speed, counter, and in particular, but not exclusively, a multi-modulo counter.
Counters may be used to count operations, quantities, or periods of time. They may also be used for dividing frequencies, for addressing information in storage, or for temporary storage. They are typically used in phase locked loop circuits. Counters consist of a series of flip-flops connected together to perform the type of counting desired. They can count up or down by ones, twos, or more.
The total number of counts or stable states a counter can indicate is called the modulus. The term modulo is used to describe the count capability of counters; that is, modulo-16 for a four-stage binary counter, modulo-11 for a decade counter, modulo-8 for a three-stage binary counter, and so forth.
There are two basic types of counter: synchronous and asynchronous. Synchronous counters typically consist of a chain of JK flip flops. The input clock pulses are applied to each flip flop. The output count is taken from the Q output of each flip flop. A high is asserted on the J and K inputs of the first flop-flop to ensure that this flip flop toggles on the falling edge of the clock pulses. Additional gates are added to ensure that the flip-flops toggle in the proper sequence. In a synchronous counter, the flip flops all toggle at the same time at the clock frequency. This arrangement prevents errors, but also results in a relatively high power consumption, especially at high frequencies. In modern communications circuits, such as for SONET circuits, clock frequencies of 600 MHz are common, and at such frequencies power consumption can be unacceptably high.
In synchronous circuits, the maximum speed is set by the combinatorial logic between a register output and a register input and the internal register hardware. Synchronous circuits require more interconnectivity. This creates extra gate loads and wire loads on drivers. This requirement limits the maximum theoretical speed for synchronous designs. A 16 bit high speed counter requires careful design of ripple and carry look-a-head structures. The least significant bit, which is also the fastest in its output rate, controls many nodes. Without a buffer the load for the driver is high, with a buffer the buffer load is still high, and the buffer introduces delay.
While synchronous circuits can be pipelined, which more or less avoids the previous loading problem, this is done at the cost of a tremendous hardware overhead. This in turn translate into high power consumption and real estate usage. In addition, some situations do not allow pipelining, for instance, the need for short duration feedback loops.
Ripple counters are so named because the events (setting and resetting of the flip flops) occur one after the other rather than all at once. The count is asynchronous, it can produce erroneous indications when the clock speed is high due to race effects. A high-speed clock can cause the lower stage flip flops to change state before the upper stages have reacted to the previous clock pulse. The errors are produced by the inability of the flip flops to keep up with the clock. Prior art ripple counters are not suitable for use at frequencies in the 600 MHz range. However, because the downstream flip flops are effectively being clocked at a lower rate, the power consumption of ripple counters is relatively low compared to synchronous counters.
The invention relates to novel high speed, multi-modulo counters based on ripple counters that are useful for high speed operations. This permits a reduction in power consumption relative to synchronous counters. In certain applications, the high speed performance of the asynchronous counters in accordance with the invention can approach that of synchronous counters.
The ripple counters in accordance with embodiments of the invention are suitable for use in phase locked loops, for example, in SONET chips. Such counters inherently have a lower power consumption and extremely high speed. A typical maximum speed is determined by the delay of a normal optimized T-flip-flop plus two NAND2 gates.
According to the present invention there is provided a high speed digital ripple counter comprising a chain of counter cells comprising a first counter cell and a series of subsequent counter cells, each of said first counter cell and said subsequent counter cells comprising a filp-flop having a master latch and slave latch, each said master and slave latch being provided with data and gating inputs: each said subsequent counter cell including a gating circuit having an output supplying gated clock signals to the gating inputs of the master and slave latches associated with that counter cell; each said gating circuit of said subsequent counter cells having a first input connected to receive signals applied to the gating inputs of the preceding counter cell and an enable input connected to an output of the master latch of the preceding counter cell; and a clock input for providing clock signals to the gating inputs of said first counter cell.
Clock gating can be employed to spread the active edges in time. This in turn spreads the load on the supply lines, which is in general good for a chip, creating less problem with noise, electromigration, and permitting the use of smaller supply lines etc.
By taking the clock signal from the output of the master latch, problems due to race effects in ripple counters can be overcome.